For more information about Carbon Design Systems, please visit
www.

refinement primer

PRESS RELEASE Reminder - Carbon to Show VSP(TM) - CoWare (TM) SPW Demo at GSPx Conference

, Synopsys, Inc.
"Making source-code to Synopsys' implementation of the VMM Standard
Library available is a big step toward driving wide adoption of
SystemVerilog ," said Michael Garcia, design and verification methodology
manager at Freescale Semiconductor.

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SystemVerilog
Catalyst Program members can provide compiled, object-code versions of the
library to their customers .; ARM KK; ARM Korea Ltd.

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What

At the GSPx Conference, Carbon Design Systems is demonstrating its virtual
system prototyping software product, VSP, with CoWare's SPW product, which
brings together multiple levels of design abstraction into one common
environment for electronic design validation.

The company is headquartered at 375 Totten Pond Road, Suite 100/200,
Waltham, MA.

About the SystemVerilog Catalyst Program
Synopsys' SystemVerilog Catalyst Program promotes the development and use
of EDA tools, verification IP and training services supporting the
SystemVerilog standard for design and verification.

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About Carbon Design Systems

Carbon is delivering a high-performance virtual system prototyping product
that enables designers to easily validate their hardware and software
months before silicon.

Carbon Design Systems and VSP are trademarks of Carbon Design Systems,
Incorporated.

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; ARM
Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co.;
and ARM Physical IP, Inc.

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Who

Carbon Design Systems, an innovator in Electronic System Level (ESL) tools
for system validation, based in Waltham, MA.

For more information about GSPx, please visit www.

Synopsys Discovery Verification Platform
The Discovery(TM) Verification Platform is a unified environment that
provides high performance and efficiency of interaction among all platform
components, including mixed-HDL simulation, mixed -signal, system-level
verification, assertions, DesignWare(R) verification intellectual property,
code coverage, functional coverage, testbenches and formal analysis.; AXYS GmbH; ARM Embedded Technologies Pvt. Ltd.

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Carbon's unique compilation technology enables high-performance, Register
Transfer Level (RTL) accurate models to be included in an ESL validation
environment.
SystemVerilog Catalyst Program members may also license the VMM Standard
Library source code at no additional cost to facilitate compatible methodology
support for their EDA tools, verification IP and services.

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Models can include: 'C,'
SystemC, RTL Verilog and VHDL, Instruction Set Simulators (ISS), and
transaction-level models .CarbonDesignSystems. VMM
Standard Library source code, which can be used with EDA tools compliant with
IEEE P1800 SystemVerilog, is planned to be available for license at no
additional charge by VCS users and SystemVerilog Catalyst members before the
end of the year. Corporate members of the
SystemVerilog Catalyst Program may gain access to Synopsys' design and
verification tools including: VCS, HDL Compiler(TM), the front-end language
compiler for Design Complier(R), and Leda (R) for the purposes of developing
SystemVerilog-based tools, ensuring their interoperability and providing
support for mutual customers.

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carbondesignsystems. Synopsys' implementation of the VMM Standard
Library is based on IEEE P1800 SystemVerilog for easy tool interoperability,
and has been extensively tested with the VCS solution. is a world leader in electronic design automation (EDA)
software for semiconductor design.com

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gspx.

NOTE: Synopsys, DesignWare, Design Compiler, Leda , OpenVera, and VCS are
registered trademarks of Synopsys, Inc.

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today. Combined
with support for industry-standard hardware design and verification languages,
including Verilog, VHDL, SystemVerilog , SystemC(TM) and OpenVera(R) and
Synopsys' proven Reference Verification Methodology, the Discovery
Verification Platform helps designers achieve higher levels of verification
productivity by contributing to first-time silicon success within required
project cycles.

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com. Problems can be found and resolved before fabrication --
rather than waiting for FPGA prototypes to be built or silicon to be
delivered .890.

Synopsys Announces Source-Code License for SystemVerilog Verification Library

; ARM Belgium N .

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890.1711, Email:
www. VMM Standard Library Enables Adoption of Techniques in the ARM-Synopsys
Verification Methodology Manual (VMM) for SystemVerilog

MOUNTAIN VIEW, Calif. ARM is a registered trademark of ARM Limited.;
AXYS Design Automation Inc.

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1500, Fax: 781.
(Nasdaq: SNPS), a world leader in semiconductor design software, today
announced the availability of the SystemVerilog source code for its
implementation of the VMM Standard Library, a base-class library to accelerate
the adoption of the SystemVerilog standard for verification.synopsys. All other trademarks or registered trademarks
mentioned in this release are the intellectual property of their respective
owners .

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com. Telephone: 781.
"By making their implementation of the VMM Standard Library available as
source code, Synopsys is providing a jump-start to designers to use the
verification techniques contained within the VMM for SystemVerilog," said
Tim Holden, director, EDA relations, ARM. "This will enable a high degree of EDA
tool interoperability, particularly with the advanced capabilities of
SystemVerilog, thereby improving verification productivity and helping to
achieve first-silicon success with even the most challenging chips."
"Synopsys has been on the leading edge of SystemVerilog from the very
beginning, when our donations accelerated the development of the language's
verification features," said Rich Goldman, vice president, Strategic Market
Development at Synopsys.

CONTACT:
Renae Veiga
Synopsys, Inc.

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The VMM Standard
Library is specified in the ARM-Synopsys book Verification Methodology Manual
for SystemVerilog, announced by Springer Science + Business Media, Inc."
Synopsys' VCS(R) comprehensive RTL verification solution includes the
object code for the VMM Standard Library. VCS customers may license the source
code at no additional cost to gain insight into the implementation details.

About Synopsys
Synopsys, Inc . Ltd.

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com."

Availability
VMM Standard Library object code is available today for VCS users. Synopsys is headquartered in
Mountain View, California and has offices in more than 60 locations throughout
North America, Europe, Japan and Asia.seifert@edelman.

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When/Where

Tuesday , October 25, 1:00 PM to 6:00 PM
Wednesday, October 26, 10:00 AM to 6:00 PM
ESL Pavilion (Booth 101)
Santa Clara Convention Center, Santa Clara, California

Information and Contacts

GSPx

To arrange a demonstration time or appointment with Carbon, please contact
Mike Whalen at mikew@carbondesignsystems.com. "This will enable our Partners to
apply sophisticated SystemVerilog verification methodologies to their ARM(R)
technology-based designs and will benefit other SoC designers in the
electronics industry as a whole by offering a way of standardizing
verification.

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Carbon's approach shortens schedules and accelerates time-to-profit by
enabling software validation to occur in parallel with hardware
development.com/ .

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Not only can 'C,' SystemC, RTL, IP cores, and
transaction-level models be validated together, but Carbon's validation
platform has the speed to execute billions of clock cycles on the RTL to
thoroughly test the hardware and software content of a design. 02451.

The library enables users to adopt the advanced verification techniques and
methodology advocated in the book more quickly and easily. Visit Synopsys online at
http://www.
"ARM" is used to represent ARM Holdings plc; its operating company ARM
Limited; and the regional subsidiaries ARM INC.

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All other companies and products referenced herein are
trademarks or registered trademarks of their respective holders .com

Sarah Seifert
Edelman
+1-650-968-4033
sarah.

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The company delivers technology-leading
semiconductor design and verification platforms and IC manufacturing software
products to the global electronics market, enabling the development and
production of complex systems-on-chips (SoCs). Synopsys also provides
intellectual property and design services to simplify the design process and
accelerate time-to-market for its customers.

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"We continue that leadership by co-authoring the VMM
for SystemVerilog book with ARM and by making our implementation of the VMM
Standard Library freely available to the industry.
+1-650-584-1902
renae@synopsys .

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Discovery and HDL Compiler are
trademarks of Synopsys, Inc.V.