Three products in the
CT3600 family provide a range of price /performance options.com/databahn . Telephone: 650-461-7200. announced the 5. The
first time, Synfora ran the tool and provided RTL to us. is the
leading provider of application engine synthesis (AES ) software used
to design complex systems-on-chips (SoCs).S.

ariola arun

This
eliminates external interface chips such as FPGAs typically found in
single-purpose DSPs with slow general-purpose I/Os further reducing
board space and system cost. For more
information about the company call 408-636-5000 or visit
www.com

It also
provides an on-chip multi pattern generator, a PRBS error checker to support
BIST, a programmable receive equalization and adjustable output pre-emphasis.

is a privately held fabless semiconductor
company specializing in innovative high speed mixed signal IC products. PICO Express 5.

abreu arun

Cradle is the only supplier of
Multiprocessor DSP solutions consisting of multiple DSP cores,
multiple general-purpose processors (GPP) and a programmable I/O
subsystem .
Coupled with a Rapid Development System and suite of IP software
functions, Cradle provides OEMs with all the building blocks necessary
to enable flexible yet high-performance DSP designs. The SATA IP core is integrated to the TaraCom SATA PHY IP
products. Its Databahn Design IP products offer fully configurable
design cores for complex interfaces such as Serial ATA and DDR-based memory
systems. Telephone: 408-530-8272.264,
WMV), imaging (photo-quality printing), wireless (3GPP ), and security
(AES) applications. The unique ability of PICO Express to take
complex C algorithms and automatically create an efficient,
flow-controlled, network of hardware accelerators is crucial for
managing this implementation complexity.

rigal artemov

Highest Single-Chip DSP Performance

The first member of the family, the CT3616, can encode 16
real-time MPEG-4 channels (480fps) at SIF resolution , sixteen G. Other features are configurable and programmable to offer the
system architect extensive flexibility for optimal performance for a
particular application. A cumulative coverage database capability
ensures that the overall test plan sufficiently exercises the design.synfora.

categorical hierarchies

264 main profile video encoder for
next-generation IP TV head-ends, surveillance DVRs and media gateways.

Family Member CT3608 CT3612 CT3616

DSP Cores Eight Twelve Sixteen
--------------------------------------------------
GPP Cores Four Six Eight
--------------------------------------------------
Programmable I/O 128 144 144
--------------------------------------------------
Data Memory 256KB 256KB 256KB
--------------------------------------------------
Speed Grades 230, 300, 230, 300, 230, 300,
375 MHz 375 MHz 375 MHz
----------------- ---------------------------------
Availability - Q305 Q305 June 05
Samples
--------------------------------------------------

The uniquely programmable I/O subsystem delivers up to 144
intelligent I/O pins for fast and flexible interconnect.

Pricing and Availability

Version 5.IP Vendors Team to Deliver Digital Controller IP, PHY IP, and Verification IP

PALO ALTO, Calif.01 now also gives designers improved correspondence
between C and RTL.

Founded in 2003, Synfora, Inc.

ariola aalst

This is
exactly what customers need to achieve a high-quality design under tremendous
time-to-market pressures.denali. is the world's leading provider of EDA tools and
Intellectual Property (IP) solutions for chip interface design, integration
and verification.com

The results
were competitive and the RTL was delivered much faster than the time
forecast for a design by hand.
PICO Express 5.01 continues to leverage the benefits of its
unique PPA architecture to ensure first pass-timing and physical
closure, and automatic creation of a thorough unit-level verification
test bench.com

Synfora, the Synfora logo, and PICO Express are trademarks of
Synfora, Inc .

lennart rewriting

0 of the Software Development Kit and the RDS3600
Digital Media Development Board will be available in June 2005,
enabling design starts for all three members of the CT3600 family., Denali Software , Inc. PICO Express automatically generates SystemC
"wrapped" models at multiple levels, for accurate modeling and
validation of a network to hardware accelerators within the system
context. The co -simulation of RTL with SystemC lets a designer
analyze the detailed parallelism of the RTL, and validate the
multi-threaded interface between the hardware accelerator and the
application processor. This is beneficial when there are concerns about
engineering change orders, and when a designer wants to understand
what the compiler has done so as to improve the input code. The
compiler in PICO Express performs powerful analyses and extensive
optimization to exploit parallelism and find the most efficient
implementation.

semantics zena

After being initially skeptical, we have been
amazed with both our design productivity and the CT3616 performance
scalability. Target applications include high
speed backplanes, 10G and 40G Ethernet, Fiber Channel, for the SAN (Storage
Area Networks) and NAS (Network Attached Storage) storage markets as well as
the recently evolving SATA (serial ATA ), SAS (serial SCSI), PCI Express and
HyperTransport applications for internal serial data communications in PCs,
servers and DAS (Direct Access Storage).
PICO Express 5.

assertion sameer

INSPECTOR(TM), the industry 's first multi-core development and
graphical debugging environment, provides unique debugging ,
profiling and performance monitoring functions for up to 24
processors simultaneously while achieving complete source code
and single stepping/breakpoint control of each processor . The
CT3600 family addresses the performance and integration requirements
of the high-performance imaging market including multi-function
printer and scanner products, film processing equipment and
machine-vision systems.
Composite configurations by port and function are also supported.

com. PICO Express empowers electronic system-level
(ESL) design methodologies by creating flow-controlled networks of
hardware accelerators from sequential C algorithms. All other names mentioned are trademarks , registered
trademarks, or service marks of their respective companies.

artemov sameer

The
CT3616 device will be sampling in June 2005 and is priced as low as
$72 in 10K quantities for the slowest speed grade . The other two
CT3600 members will be sampling in Q305 and are priced as low as $40
in 10K quantities . Cradle's
corporate headquarters are located in Sunnyvale, California.5Gb/s, with
next-generation speed increases of 3Gb/s and beyond.

About Denali
Denali Software Inc.

About TaraCom
TaraCom Integrated Products Inc. The
company's high performance products offer industry's highest jitter tolerance
and most comprehensive features to address the requirements of LAN/MAN/WAN/SAN
markets with a wide variety of applications.264."

About PICO Express 5.

categorical rewriting

Business Editors/High-Tech Editors

SUNNYVALE, Calif. An
optionally integrated Databahn double data rate (DDR) memory controller core
keeps SATA data off the system busses, lowering CPU overhead.
The highly integrated nature of PureSpec for SATA's model behavior and data
generation engine applies a sophisticated context-sensitive data generation
approach to test plan execution . Synfora's patented
technology helps to reduce fixed design costs and dramatically speed
chip development and time-to-market.

saman agrawal

The CT3616
device also enables the industry's first programmable DSP-based
single-chip real-time D1 H. The CT3600 MDSP slashes development time when compared to
prior multi-core DSP chips or other hardware-based parallel
architectures through its innovative multi -processor architecture
coupled with two key technologies: a multi-core debugger and an
intermediate -level compiler for DSP task optimization. It also is ideal for the emerging multi-codec
and multi -function requirements of the broadcast + IP TV head-end
market including encoding, streaming and transcoding equipment, media
gateways, video conferencing systems and video phones.com.

For more information, please contact:
Nanette Collins
Public Relations for Denali Software
617-437-1822
nanette@nvc. PICO
Express helped us to meet our tapeout deadlines with silicon optimized
for our highly competitive markets. For
performance targets that require further parallelism, multiple buffers
will be inserted automatically for shared arrays to allow multiple
tasks to run in parallel.
PICO Express 05.

rewriting jordanstown

This is 4X better than other programmable
multimedia DSPs in the market today. "We
have had early access to the toolset to implement our popular MPEG4
codec on the CT3616.
The integrated solution provides developers with Denali's Databahn(TM )
design IP for controlling SATA devices, TaraCom's TRC3002 SATA physical layer
(PHY) IP, and Denali 's PureSpec(TM) verification IP for ensuring compliance,
interoperability and system performance.

For more complete information about TaraCom SATA PHY products, visit
TaraCom online at: http: //www. For more information, visit TaraCom
at http://www.net.net

NOTE: The Denali logo , Denali, and Databahn, PureSpec, and MMAV are
trademarks of Denali Software Inc. of Mountain View , Calif.

maximillians rewriting

About Cradle Technologies

Cradle is a fabless semiconductor company providing the highest
performance, most flexible multiprocessor DSP solutions for real-time
video, audio and imaging applications."

About Denali Databahn SATA Controller IP Products
Denali 's Databahn SATA core supports Serial ATA 1.5Gb/s and 3Gb/s,
and other optional features such as Native Command Queuing (NCQ). Injected errors and
error conditions are flagged and recovered according to SATA specifications.
"Many companies are working to implement complex algorithms in
silicon , for example, H.01 is the only
tool that can produce designs with that complexity. The improved correspondence eases the mapping of C
operators and variables to RTL constructs.

maximillians categorical

50 per channel (MPEG4 SP
L3) , more than 2X better than the closest competition.

Today's Very Long Instruction Word (VLIW) parallel DSP chips
require time-consuming assembly code optimization to achieve
high performance. "By working with TaraCom, we will be providing the
additional value of a highly integrated solution that spans all the way from
the PHY to the system interface, including system -level verification. "By joining forces on the digital controller, PHY and
verification flow, we 're able to offer customers a lot of value in terms of
performance and overall design quality. Databahn SATA
also offers a simple interface to the Direct Memory Access (DMA) interface
using the Intel advanced host controller interface (AHCI) specification, and a
programmed I/O (PIO) mode for legacy applications and AT Attachment Packet
Interface (ATAPI). Additional features
include, slumber and partial power saving modes, programmable out-of-band
signaling, far-end and near-end loopback modes, and hot plug support. All other trademarks are the property of
their respective owners. Synfora targets companies in the
audio, video, imaging, wireless, and security segments of the IC
design market. The company's investors are ATA Ventures, Foundation
Capital, and U.

maximillians moniz

It delivers
new price /performance points for the rapidly expanding video
surveillance market including applications such as IP cameras and
streamers, network video recorders (NVRs) and multi-channel DVRs.
For more information about Denali's PureSpec verification IP products,
visit Denali online at http://www. The
company is focused in developing innovative technologies to design and market
high speed, high performance SerDes (Serializer, Deserializer), physical
interface ASSP and IP core products using sub-micron CMOS process.

Business Editors/High-Tech Writers

MOUNTAIN VIEW, Calif .264, WMV, and 3GPP.01 automatically analyzes sequential code blocks to
determine if they should run sequentially or in parallel.

moniz ariola

Most Flexible, Integrated and Scalable DSP Platform

"The CT3600 family uniquely integrates multiple general-purpose
processors (GPP) alongside multiple DSPs , thereby improving processor
efficiency of control, data flow and networking stack functions
required in today's multimedia applications," said Kourosh Amiri,
director of product marketing for Cradle . "Integration of multiple
video and audio codecs, all of the control + network stack processing
and a unique programmable I/O subsystem into a single multimedia DSP
reduces board space up to 75% and system cost up to 50%.0 of Cradle's Software
Development Kit (SDK) and the RDS3600 Digital Media Development
Platform.0 tool set shatters the myth that multiprocessor
architectures are difficult to program," said Roger Li, Director of
Engineering at Jaxstream, a Cradle 3rd Party Alliance Partner .cradle. and
TaraCom Integrated Products Inc. The TRC3002 enables data transfer rates of 150 MB and 300 MB,
uses DDR transmission for sending and receiving data. This enables direct translation from test
plan definition to implementation, accelerating the verification task and
overall verification productivity. This addresses the
critical issue of complexity levels typical of algorithms such as
H.01, design teams can now leverage the benefits
of SystemC for system-level validation without needing to learn the
vagaries of the language.

agrawal semantics

This includes Version 5.

Denali and TaraCom Announce Comprehensive Solutions for 3.0 Gb/s SATA

About TaraCom SATA PHY Products
TaraCom's TRC3002 SATA PHY product provides a complete physical layer of
the SATA standards, with an optimized interface to the Denali Databahn SATA
controller IP.taracom. PureSpec verification IP
includes a configurable bus functional model (BFM), protocol monitor, and
complete assertion library for all SATA components in the topology, including
the host and one or more SATA devices .
Email: info@denali. It also broadens the scope
of algorithms that can be efficiently synthesized by blending highly
pipelined and sequential stages that are typically found in advanced
algorithms such as H.

maximillians assertion

711
voice channels, perform a complete IP packet encapsulation (RTP/UDP)
with a 10/100 Ethernet MAC and provide an integrated hard disk (IDE)
or compact FLASH storage interface, achieving the world's first
16-channel "digital video recorder (DVR) on-a-chip" for the
surveillance industry ."
The CT3600 product family integrates up to sixteen loosely coupled
SIMD 32-bit DSP engines, eight general-purpose CPUs, 144 programmable
I/O pins and a three-tiered memory hierarchy system to accelerate and
integrate multimedia infrastructure processing.0a at 1.taracom.
Email: fhaghighi@taracom .264 encoders, and they are challenged by
unprecedented design complexity," said Synfora CEO Simon Napper."
Thierry Bauchon, Director of R+D for the Home Entertainment Group
of STMicroelectronics , said, "We have used PICO Express on two
occasions to produce RTL code used in recent design tape -outs. For the latest news and
information on Synfora, visit www.

artemov hierarchies

Cradle Delivers Industry's Highest Single-Chip DSP Performance; Programmable DSP Family with up to Sixteen 375MHz DSP Engines Boosts Compute Power for Multimed

net .
PureSpec additionally provides a sophisticated data generation engine to help
drive defined, pseudo-random bus traffic at all layers.com/purespec .

abreu jordanstown

"The SDK V5.
"Design teams are increasingly looking for best-in-class IP solutions for
deploying complex interface standards such as SATA," says David Lin, vice
president at Denali."
"Our customers view this integrated SATA solution as a critical piece of
the puzzle for their chip designs," adds TaraCom Chief Executive Officer
Farhad Haghighi.
For more information about Denali's Databahn SATA IP, visit Denali online
at http://www. Denali's PureSpec Verification IP product supports all complex
interfaces, including PCI Express, Advanced Switching Interconnect (ASI), USB,
Ethernet and Serial ATA.denali.

lennart rigal

Serial ATA is quickly replacing parallel ATA in hard disks in desktop and
mobile PCs. Design teams are now
using IP from Denali and TaraCom as building blocks for rapidly deploying
high-quality SATA designs for next-generation electronics products.----April 26,
2005--Synfora (TM), Inc. "It's
not enough to move to a higher-level language; they need to move to a
higher-level capability.01

PICO Express 5. In addition, PICO Express 5.01 supports data
paths greater than 32-bits by supporting co-scheduling of multiple
streams of data.

maximillians lennart

The CT3616 is the industry's best
price/performance encoding solution at $5.
Embedded hardware in the chip acts in concert with INSPECTOR
to provide complete visibility into global/local variables,
registers , and data memory and activity of all processors. The SATA hard drive connector is smaller than the equivalent
parallel connector, and enables data transfer rates of 1. The integrated flow also enables us
to provide the configurability needed to address specific markets and
applications. More than 400 companies worldwide use Denali's
tools, technology and services to design and verify complex chip interfaces
for communication, consumer, and computer products. For more information,
visit Denali at http://www. The new release
features enhanced capabilities for solving implementation challenges
inherent in state-of-the-art algorithms found in multimedia (H.

aalst lennart

Complete Tool Set Slashes Development Time

In conjunction with the release of the CT3600 product family,
Cradle is announcing the availability of a complete CT3600 development
environment. Cradle's multiprocessor DSP
architecture innovation delivers high-performance scalable DSP
processing with the flexibility, time-to-market and product
differentiation benefits of processor-based programmable platforms., a leading provider of SerDes technology,
today announced availability of comprehensive intellectual property (IP)
solutions for Serial ATA (SATA) design, verification, and deployment.

About Denali PureSpec Verification IP for SATA
PureSpec for SATA is a comprehensive solution for verifying functionality,
compliance , and interoperability of all Serial ATA speeds and designs at the
pre-silicon stage of chip or IP core development.

Major New Release of Synfora PICO Express Cuts Time and Cost of Producing Complex Consumer System-on-Chip Designs

01 release of PICO Express(TM)
for application engine synthesis (AES), which is used to greatly
accelerate the design of systems-on-chips (SoCs). More than one year later , our
requirements changed, and we were able to pick up the original C
algorithm and make the required changes in less than a day.01 expands the networks of hardware accelerators
that can be synthesized from C algorithms. As a result, designers can
now create more sophisticated networks of hardware accelerators.
With PICO Express 5. PICO Express also supports SystemC and Verilog RTL
co-simulation . Venture Partners.

jordanstown artemov

----Cradle
Technologies, Inc., a pioneer in high-performance multiprocessor DSP
platform solutions for real-time multimedia, today announced three
products in its new CT3600 product family, realizing a Multiprocessor
DSP vision that delivers the industry's highest single -chip DSP
performance and most scalable price/performance DSP platform for
embedded multimedia applications.
The CT3616 offers 24000 MMACs (Million Multiply-Accumulates) or
275MMACs per dollar . Cradle's CLASM(TM) -- a C-based
intermediate-level compiler for timing-critical DSP task
optimization -- delivers predictable design performance while
reducing tedious low-level assembly optimization typically
required when using VLIW C-compilers."

Markets and Applications

The CT3600 family dramatically expands the market opportunities of
the initial CT3400 Multiprocessor DSP family from Cradle.denali.

About Synfora, Inc.