Aldec will provide a
demonstration of the advantages and strategies for using each of these
system-level design languages using both Active-HDL and Riviera.

Register for a Demonstration

To schedule some time to view Aldec 's solutions, please visit

http://register., a 21-year EDA tool provider, is committed to
delivering high-performance, HDL-based design verification software
for UNIX, Linux and Windows platforms.

dependant synopsys

In one recent project, we found benefit by relying on NTB's
constraint solver to create complex test sequences versus the traditional
approach of writing directed tests.com, for Synopsys; or Vicki McCann of Atmel Corporation,
+1-719-540-1724, or vmccann@cso.

System Level Platform

Aldec will be presenting its new generation of system level design
capabilities and several advanced features for private viewing during
the show. Additional information about Aldec is
available at http: //www.

synchronicity designworks

About Atmel
Atmel is a worldwide leader in the design and manufacture of
microcontrollers , advanced logic, mixed-signal, nonvolatile memory and radio
frequency (RF) components. All other trademarks or
registered trademarks mentioned in this release are the intellectual property
of their respective owners.seifert@edelman.

DSP Solution

Many DSP designers use MATLAB to create a model of the signal
processing application before it is implemented and MATLAB simulations
with Simulink are often used to test the DSP behavior.3 versus
Mentor's ModelSim see the report on DeepChip at
http://www.

simulink iteration

By natively integrating a comprehensive set of bug-finding
technologies , the VCS solution offers up to 5x faster verification performance
compared with using stand-alone tools.3 Crushes Mentor
ModelSim"
To read what customers have to say about Active HDL 6.com/items /0445-07.

autorouting uniformity

SystemVerilog assertions are written
by designers to capture elements of the verification plan, enabling progress
to be tracked over time and increasing confidence in verification schedules .
"SystemVerilog assertions in particular have quickly become an important part
of our verification and debug strategies, and are being eagerly adopted by our
design teams. Discovery is a trademark of Synopsys, Inc.

System Level Language

A key element of system-level design and verification is the
ability to describe the system in a higher, more efficient language
structure.aspx

Latest ESNUG Report Says "Aldec Active-HDL 6.

simulink jesa

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Latest ESNUG Report Says "Aldec Active -HDL(TM) 6. Anticipated release of the solution is scheduled for Q3 of
2005.

ruplan autorouting

simulink uniformity

VCS Native Testbench Technology Helps Atmel Find Critical Bugs in Less Time

MOUNTAIN VIEW, Calif.

Business Editors
Design Automation Conference 2005
Booth #1023

HENDERSON, Nev. All other trademarks or registered
trademarks are property of their respective owners.

ruplan elcad

All necessary
libraries, compilers and debugging tools are included at no extra cost
with standard versions of Aldec verification products . SystemC testbenches are typically
10 to 100 times faster than VHDL and Verilog testbenches due to the
higher level of abstraction in SystemC.html

About Aldec

Aldec, Inc.

promis designworks

zuken pspice

The company delivers technology-leading
semiconductor design and verification platforms and IC manufacturing software
products to the global electronics market, enabling the development and
production of complex systems-on-chips (SoCs).com; or Sarah Seifert of Edelman, +1-650-968-4033, or
sarah.

synopsys promis

"With full-featured testbench
capabilities, built-in assertions and a wide range of coverage metrics,
customers such as Atmel are achieving much better verification results with
less effort in less time.

EDA = Electronic design automation

socs simulink

(Nasdaq: SNPS), a world leader in semiconductor design software, today
announced that Atmel Corporation (Nasdaq: ATML), a global leader in the
development and fabrication of advanced semiconductor solutions, has adopted
the latest release of Synopsys' VCS(R) comprehensive RTL verification solution
for verification of its leading devices.

NOTE: DesignWare, OpenVera and VCS are registered trademarks of Synopsys,
Inc.

CONTACT: Isela Warner of Synopsys, Inc. Also included
are complete C++ programming capabilities, testbench-specific
libraries for efficiently creating HDL testbenches, and
standards-based reuse of the code.aldec.

systemc schematic

, +1-650-584 -1644, or
igamboa@synopsys.

uniformity 3001

"
"The wealth of bug-finding technologies in VCS makes it a truly
comprehensive RTL verification solution," said Farhad Hayat, vice president of
Marketing, Verification Group, Synopsys, Inc. Synopsys also provides
intellectual property and design services to simplify the design process and
accelerate time-to-market for its customers. Leveraging one of the industry 's broadest
intellectual property (IP) technology portfolios, Atmel is able to provide the
electronics industry with complete system solutions.deepchip.

synopsys autorouting

Atmel Adopts Synopsys' VCS Native Testbench and SystemVerilog Assertions

com/Registration/DAC/DAC2005.

fabless jesa

"The availability of native verification
technologies in a single tool allows us to easily deploy advanced verification
techniques. Using the tool to exercise the part saved
us time and resources, found bugs and let us run more cycles.

C/C++ Testbench Automation

Aldec will present a complete, automated environment for writing
and executing C/C++ testbenches for verification. Aldec is dedicated and
responsive to serving its customers' needs with its offices located
around the globe. Continuous innovation, superior product quality and
total commitment to customer service comprise the foundation of
Aldec's strategic objectives.com
Active -HDL, Riviera and Incremental Prototyping Technology are
trademarks of Aldec, Inc.

ruplan elcad

, Synopsys, Inc .

stripboard jesa

"We make extensive use of the VCS solution's built-in coverage features to
help monitor progress to our verification plan," continued Eric Costello.synopsys., a pioneer in mixed-language simulation and advanced
design tools for ASIC and FPGA devices, today announced the new
products and solutions it will be displaying at the 2005 Design
Automation Conference (DAC) at booth #1023 in Anaheim, California ,
June 13-17.

jesa powerstation

The combination of the VCS solution's native assertion, testbench and
comprehensive code coverage engines provides an effective mechanism for
tracking verification progress and effectiveness.

About Synopsys
Synopsys, Inc. Visit Synopsys online at
http://www. Focused on consumer,
industrial, security, communications, computing and automotive markets, Atmel
ICs can be found Everywhere You Are(SM).

zuken stripboard

"
Atmel also takes advantage of the VCS solution's built-in support for
SystemVerilog assertions, functional coverage and code coverage as part of a
coverage-driven verification methodology.

Aldec to Showcase New Verification Products and Solutions at DAC 2005 Booth #1023

Aldec will
provide a demonstration using Active-HDL and Riviera in conjunction
with MATLAB and Simulink for co-simulation and testing of HDL and DSP
designs .

pspice fabless

Atmel development teams are taking
full advantage of the built-in verification features of the VCS solution,
including Native Testbench (NTB) technology, SystemVerilog assertions, and
built-in coverage.atmel.3 Crushes
Mentor(R) ModelSim(R)"

Aldec, Inc.

fabless powerstation

The VCS solution is a key component of
the Synopsys Discovery(TM) Verification Platform.
"VCS' NTB has been easy to adopt and has proven itself by providing
increased productivity in validating our designs," said Eric Costello, design
methodology manager at Atmel. is a world leader in electronic design automation (EDA)
software for semiconductor design. Features include:

SystemC and SystemVerilog language support

High-level C++ testbench engine

System level design entry (ESL)

64 -bit simulation engine supports VHDL, Verilog 2001, EDIF,
SystemVerilog

Complete debugging environment with assertions support (OVA,
PSL, SVA)

Mixed Digital/Analog Simulation

Aldec will be showing a private demonstration of an all new
system-level mixed analog/digital simulation solution. The solution is
based on Aldec's industry-proven VHDL, Verilog and SystemVerilog
mixed-language simulation technology and the Turbo Spice simulator for
new generation system-on -chip designs. These higher-level languages include SystemC, C/C++,
SystemVerilog and assertion-based verification.

geda pspice

Synopsys is headquartered in
Mountain View, California and has offices in more than 60 locations throughout
North America, Europe, Japan and Asia.com/.com

dependant speedcad

"

Synopsys Discovery Verification Platform
The Discovery Verification Platform is a unified environment that provides
high performance and efficiency of interaction among all platform components,
including mixed-HDL simulation, mixed-signal, system-level verification,
assertions, DesignWare(R) verification intellectual property, code coverage,
functional coverage, testbenches and formal analysis. Combined with support
for industry-standard hardware design and verification languages, including
Verilog , VHDL, SystemVerilog, SystemC(TM) and OpenVera(R) and Synopsys' proven
Reference Verification Methodology , the Discovery Verification Platform helps
designers achieve higher levels of verification productivity by contributing
to first-time silicon success within required project cycles.aldec.

geda schematic

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